RISC and CISC

Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC)

CISC - complex instruction set computer

The term "CISC" (complex instruction set computer or computing) refers to computers designed with a full set of instructions that were intended to provide needed capabilities in the most efficient way. Later, it was discovered that, by reducing the full set to only the most frequently used instructions, the computer would get more work done in a shorter amount of time for most applications. Since this was called reduced instruction set computing (RISC), there was now a need to have something to call full-set instruction computers - thus, the term CISC.

RISC - reduced instruction set computer

A type of microprocessor design that focuses on rapid and efficient processing of a relatively small set of instructions. RISC architecture limits the number of instructions that are built into the microprocessor, but optimizes each so it can be carried out very rapidly-usually within a single clock cycle.

Note:

The early microprocessors (such as the Intel 4040 in some ways could be considered RISC processors as they had a very limited set of instructions. As the processors became more complex (such as the Intel 80386), the number of instructions also increased thus earning the title of CISC processors. However, these early processors did not have the large number of registers and the ability to pipeline data and instructions which are key components of the RISC processors.

More Information

From http://www.intel.com

What are CISC and RISC? How do they affect users?
CISC (Complex Instruction Set Computing) and RISC (Reduced Instruction Set Computing) are two theoretical approaches to designing microprocessors, each with its own advantages. Microprocessors like the Intel386™ were entirely CISC-based, but today’s Pentium and Pentium Pro processors include both CISC and RISC features. The superscalar design of Pentium processors and the Dynamic Execution microarchitecture of Pentium Pro processors offer functionality that is similar to RISC microprocessors while offering a distinct advantage.... They are fully compatible with virtually all existing PC software.

More information courtesy Mr Steve Kessel, Curtin University

Foundations of Computer Science 151 Computer Organisation 501

Reduced Instruction Set Computers
Lecture 11

Dr. Brian R. von Konsky
Curtin University of Technology
School of Computing

Reduced Instruction Set Computers-
Reduce the complexity of the architecture to improve performance by eliminating complex operations which are used infrequently, exotic addressing modes which encourage bus traffic, and slow, horizontal, microprogrammed Control Units. Instead, implement a simple architecture designed for performance using a relatively small number of logic gates, and/or a small number of vertical microinstructions. RISC architectures are designed as integrated systems, relying on software developers and optimizing compilers for the greatest performance benefit.

The Reduced Instruction Set Computers (RISC) Philosophy

Limit time consuming traffic across the system bus-

  • Provide load and store operations in direct addressing mode only, as other more exotic addressing modes encourage slow traffic across the system bus.
  • Eliminate the instructions which people don't use often to free chip real estate.
  • Provide a large number of registers to keep the data close to the CPU where it is needed.

    • Rebalance the responsibilities of hardware and software-

  • Improve compiler technology to optimize register usage.
  • Optimize instruction pipeline to take greater advantage of pipe lining.

    • Improve architectural efficiency by considering if complex instructions should be procedures in software libraries in main memory or in microprograms in control store.

  • Imbalance between memory and CPU performance using older implementation technologies made implementing complex instructions in microcode very attractive.
  • While still an issue, the imbalance between memory and CPU performance is less of significant using modern technologies.
  • Programmers don't use complex instructions often.

    • Minimize Clock Cycles Per Instruction (CPI)

  • Overlap fetch, decode, execute, write-back sub-cycles.
  • Avoid pipeline stalls through smart instruction scheduling.
  • Goal is to execute one instruction per clock cycle, on the average.

    • In designing a new computer architecture, the designer is trying to reach the "best" balance between functionality and performance.

    Author: Mike Leishman